1. Technical Field
The present invention relates, generally, to amplifier biasing, and more particularly to circuit topologies for biasing an amplifier output stage for Class A, Class B or Class AB operation to achieve accurate quiescent control at the output stage, to thereby conserve power and maintain enhanced device linearity.
2. Background Art and Technical Problems
The output stage of an amplifier provides a low output resistance that enables output signal delivery to a load with minimal loss of gain. While it is the primary function of the output stage to generate the output signal with minimal loss, it is also desirable to efficiently produce the output signal with minimal total harmonic distortion (THD). This implies that the power dissipated by the output stage is minimized, while providing suitable device linearity.
In order to meet the various efficiency and linearity requirements for a given application, various biasing schemes have been proposed that are generally classified according to the collector current that results when an input signal is applied. These biasing schemes include Class A, Class B, Class C, and Class AB biasing. Class AB biasing techniques are generally desirable for applications which involve driving low ohmic loads, inasmuch as power dissipation under quiescent conditions and crossover distortion are both minimized. In order to fully exploit the Class AB biasing schemes, however, precise control of the quiescent current to the output transistors is required in a wide variety of operating conditions. However, as amplifiers are often composed of at least two stages that are internally compensated, precise control of the output load transistors becomes a difficult and complex task.
Prior art attempts to control the quiescent current through the output transistors in a Class AB amplifier have involved creating a replica of the output device, and to measure and control the quiescent current through the replica device. In this way, precise control of the output device transistor quiescent current may be achieved, to the extent the various factors influencing the quiescent current through the actual output device can be accurately replicated in the replica device.
Presently known techniques for accurately controlling output device quiescent current have thus far been unsatisfactory, in part due to the difficulty associated with appreciating and replicating the relevant operating parameters of the output devices in the context of replica devices.
For a broader discussion of Class AB amplifier biasing techniques, see the following references, the entire contents of which are hereby incorporated by reference: Bailey, et al., U.S. Pat. No. 5,654,672, issued Aug. 5, 1997, entitled xe2x80x9cPrecision Bias Circuit for a Class AB Amplifierxe2x80x9d; xe2x80x9cA Compact Power-Efficient 3 V CMOS Rail-to-Rail Input/Output Operational Amplifier for VLSI Cell Librariesxe2x80x9d, by Hogervorst, et al., in the December 1994 IEEE; xe2x80x9cA Quad CMOS Single-Supply OP Amp with Rail-to-Rail Output Swingxe2x80x9d, by Monticelli, in the December 1986 IEEE; and xe2x80x9cLow-Power Low-Voltage VLSI Operational Amplifier Cellsxe2x80x9d, by Huijsing, et al., in the November 1995 IEEE.
Methods and apparatus are thus needed for improving the parameters associated with replica devices, to thereby enhance the quiescent control of the output stage in Class AB amplifiers, which overcome the shortcomings of the prior art.
The present invention provides improved methods and apparatus for controlling the quiescent current through output devices. In accordance with a preferred embodiment of the present invention, a gate control circuit is provided which controls the gate of a xe2x80x9cfloating resistorxe2x80x9d transistor, to thereby precisely control the quiescent current of the output devices. In accordance with a particularly preferred embodiment, a gate control circuit includes a replica transistor, wherein the replica device sees the same drain source conditions as the output device. In accordance with a further aspect of this embodiment, a current source is employed to source the output replica device independent of any other replica devices.
In accordance with a further aspect of the present invention, a gate current control circuit is provided which includes a replica device which shares a common gate voltage node with its corresponding output device, as well as an amplifier for directly controlling the gate voltage of the floating resistor.
In accordance with an alternate embodiment of the present invention, an indirect quiescent bias servo circuit is provided which includes a primary floating resistor network, the output of which directly controls the gates of the output devices; in addition, the indirect quiescent bias servo circuit includes a replica structure of the primary floating resistor network, wherein the output of the replica structure is used to control the gates of the output replica devices. In accordance with a further aspect of this embodiment, the gate control circuit for controlling the floating resistor of the replica floating resistor structure includes an amplifier having an output configured to directly control the gate voltage of the floating resistor in the replica floating resistor structure.
In accordance with a further aspect of the present invention, a reduced form quiescent bias servo circuit is provided, wherein the gate control circuit includes an output replica device having its gate tied to the same voltage node as the gate of its corresponding output device. In accordance with a further aspect of the reduced form embodiment, only a single replica device (the output replica device) is provided, which allows the reduced form servo circuit to operate effectively in a 3-volt environment.
In accordance with a further aspect of the present invention, a decoupled quiescent bias servo circuit is provided which includes a first floating resistor transistor configured to control the gate voltage of a first output device, and a second floating resistor decoupled from the first floating resistor and configured to control the gate voltage of the complimentary output device. In accordance with this decoupled embodiment, problems associated with the unequal affects of current sources and other affects on the two complimentary floating resistors are eliminated.
In accordance with a further aspect of the present invention, an NMOS-coupled quiescent bias servo circuit is provided which further enhances the decoupled servo circuit by providing an NMOS current mirror to ensure correspondence between the current used to drive the first floating resistor and the current used to drive the second floating resistor which is decoupled from the first floating resistor.
In accordance with a further aspect of the present invention, a PMOS-coupled quiescent bias servo circuit is provided which includes a PMOS current mirror to provide current to the decoupled floating resistor transistors.